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dual 3 mhz, 1200 ma buck regulators with one 300 ma ldo data sheet ADP5024 rev. e document feedback informat ion furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications sub je ct t o cha nge wi thout not ice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, no rwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2011 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com f eatures main input voltage range: 2.3 v to 5.5 v two 1200 ma buck regulators and one 300 ma ldo 24- lead, 4 mm 4 mm lfcsp package regulator a ccuracy: 1.8 % factory programmable or external adjustable voutx 3 mhz buck operation with forced pwm and auto mat ic pwm/psm modes buck1/buck2: output voltage range from 0.8 v to 3.8 v ldo : output voltage range from 0.8 v to 5.2 v ldo : input supply voltage from 1.7 v to 5.5 v ldo : high psrr and low output noise applications power for processors, asics, fpgas, and rf c hipsets portable instrumentation and medical devices space constrained devices general description the ADP5024 combines two high performance buck regula - tors and one low dropout (ldo) regulator i n a small, 24 - lead , 4 mm 4 mm lfcsp to meet demanding performance and board space requirements. the high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space. when the mode pin is set high, the buck regulators operate in forced pwm mode. when the mode pin is set low, the buck regul ators operate in pwm mode when the load current is above a predefined threshold . when the load current falls below a pre - defined threshold, the regulator operates in power save mode (psm) , improving the light load efficiency. table 1. family models model channels maximum current package adp5023 2 buck, 1 ldo 800 ma, 300 ma lfcsp (c p - 24 - 10) ADP5024 2 buck, 1 ldo 1.2 a, 300 ma lfcsp (cp - 24 - 10) adp5034 2 buck, 2 ldos 1.2 a, 300 ma lfcsp (cp - 24 - 10), tssop (re - 28 - 1) adp5037 2 buck, 2 ldos 800 ma, 300 ma lfcsp (cp - 24 - 10) adp5033 2 buck, 2 ldos with 2 en pins 800 ma, 300 ma wlcsp (cb - 16 - 8) the tw o bucks operate out of phase to reduce the input capacitor requirement. the low quiescent current, low dropout voltage, and wide input voltage range of the ldo extends the battery life of portable devices. the ADP5024 ldo maintain s power supply rejection greater than 60 db for frequencies as high as 10 khz while operating with a low headroom voltage. regulators in the ADP5024 are activa ted though dedicated enable pins. the default output voltages can be either externall y set in the adjustable version or factory programmable to a wide range of preset values in the fixed voltage version. typical application circuit vin1 vin3 en1 pwm psm/pwm 2.3v to 5.5v sw1 fb1 r2 r1 vout1 pgnd1 mode c5 10f v out1 at 1200ma v out2 at 1200ma v out3 at 300ma l1 1h en1 buck1 mode c3 1f c2 4.7f c1 4.7f avin c avin 0.1f vin2 en2 agnd en2 buck2 mode en3 1.7v to 5.5v on off on off en3 ldo (analog) housekeeping sw2 fb2 r4 r3 vout2 pgnd2 c6 10f l2 1h fb3 r6 r5 vout3 c7 1f ADP5024 09888-001 figure 1 .
ADP5024 data sheet rev. e | page 2 of 28 table of contents features .....................................................................................1 applications ...............................................................................1 genera l description ..................................................................1 typical application circuit ........................................................1 revision history ........................................................................2 specifications .............................................................................3 general specifications ............................................................3 buck1 and buck2 specifications ........................................4 ldo specifications ................................................................5 input and output capacitor, recommended specifications ..6 absolute maximum ratings ......................................................7 thermal resistance ................................................................7 esd caution ..........................................................................7 pin configuration and function descripti ons ...........................8 typical performance characteristics .........................................9 theory of operation ................................................................ 16 power management unit ..................................................... 17 buck1 and buck2 ............................................................ 19 ldo ..................................................................................... 20 applicatio ns information ........................................................ 21 buck external component selection ................................... 21 ldo external component selection ................................... 23 power dissipation and thermal considerations ..................... 24 buck regulator power dissipation ....................................... 24 junction temperat ure .......................................................... 25 pcb layout guidelines ............................................................ 26 typical application schematics ............................................... 27 bill of materials .................................................................... 27 outline dimensions ................................................................ 28 ordering guide ................................................................... 28 revision history 5/13 r ev. d t o r ev. e added table 1 ; renumbered sequentially ................................. 1 changes to figure 1 ...................................................................1 changes to nc pin description .................................................8 changes to figure 48 ...............................................................20 changes to figure 50 ...............................................................22 changes to figure 52 and figure 53 .........................................27 1/13 r ev. c to r ev. d changes to figure 9 ................................................................. 10 changes to ordering g uide .....................................................28 1 2/12 r ev. b to r ev. c changes to ordering guide .....................................................28 11 /12 r ev. a to r ev. b changes to features section ......................................................1 changes to output voltage accuracy and vo l t a g e feedback parameters , table 2 ....................................................................4 changes to output voltage accuracy and voltage feedback parameter s , table 3 ....................................................................5 changes to figure 6, figure 7 and figure 8 ................................ 9 changes to figure 30 and figure 31 ........................................ 13 changes to figure 34 ............................................................... 14 chan ge to figure 38 ................................................................ 14 changes to undervoltage lockout section .............................. 17 cha nges to buck regulator power dissipation section ........... 24 1/1 2 r ev. 0 to r ev. a changes to features section and figure 1 ................................. 1 changes to table 2 ..................................................................... 4 changes to table 3 ..................................................................... 5 changes to table 4 ..................................................................... 6 changes to table 7 ..................................................................... 8 changes to figure 34 ............................................................... 14 changes to ldo section and figure 48 ................................... 20 changes to table 9 and figure 50 ............................................ 22 changes to buck regula tor power dissipation section ........... 24 changes to figure 52 and figure 53 ........................................ 27 8 /11 revision 0: initial version
data sheet ADP5024 rev. e | page 3 of 28 specifications general specificatio ns v avi n = v in1 = v in2 = 2.3 v to 5.5 v; v in3 = 1.7 v to 5.5 v; t j = ?40c to +125c for minimum/maximum specificat ions, and t a = 25c for typical specifications, unless otherwise noted. table 2. parameter symbol test conditions/comments min typ max unit input voltage range v avin , v in1 , v in2 2.3 5.5 v thermal shutdown threshold ts sd t j rising 150 c hysteresis ts sd - hys 20 c start - up time 1 buck1, ldo t s ta r t 1 250 s buck2 t s ta r t 2 300 s en1, en2, en3, mode inputs input logic high v ih 1.1 v input logic low v il 0.4 v input leakage current v i - leakage 0.05 1 a input current all channels enabled i stby - nosw no load, no buck switching 108 175 a all channels disabled i shutdown t j = ?40c to +85c 0.3 1 a vin1 undervoltage lockout high uvlo input voltage rising uvlo vin1rise 3.9 v h igh uvlo input voltage falling uvlo v i n 1 fa l l 3.1 v low uvlo input voltage rising uvlo vin1rise 2.275 v low uvlo input voltage falling uvlo vin1 fa l l 1.95 v 1 start - up time is defined as the time from en1 = en2 = en3 from 0 v to v avin to vout1, vout2, and vout3 reaching 90% of their nominal level s . start - up times are shorter for individual channels if another channel is already enabled. see the typical performance characteristics section for more information .
ADP5024 data sheet rev. e | page 4 of 28 buck1 and buck2 spec ifications v avi n = v in1 = v in2 = 2.3 v to 5.5 v; t j = ?40c to +125c for minimum/maximum specifications, and t a = 25c for typical specifications, unless otherwise noted. 1 table 3. parameter symbol test conditions/comments min typ max unit output characteristics output voltage accuracy v ou t1 / v out1 , v out2 / v out2 i load1 = i load2 = 0 ma ? 1.8 + 1.8 % line regulation ( v out1 /v out1 )/v in1 , ( v out2 /v out2 )/v in2 pwm mode ?0.05 %/v load regulation ( v out1 /v out1 )/ i out1 , ( v out2 /v out2 )/ i out 2 i load = 0 ma to 1200 ma, pwm mode ?0.1 %/a voltag e feedback v fb1 , v fb2 models with adjustable outputs 0.491 0.5 0.509 v operati ng supply current mode = ground buck1 only i in i load1 = 0 ma, device not switching, all other channels disabled 44 a buck2 only i in i load2 = 0 ma, device not switching, all other channels disabled 55 a buck1 and buck2 i in i load1 = i load2 = 0 ma, device not switching, ldo channels disabled 67 a psm current threshold i psm psm to pwm operation 100 ma sw characteristics sw on resistance r n fet v in1 = v in2 = 3.6 v 155 240 m r p fet v in1 = v in2 = 3.6 v 205 310 m r n fet v in1 = v in2 = 5.5 v 137 204 m r p fet v in1 = v in2 = 5.5 v 162 243 m current limit i limit1 , i limit2 pfet switch peak current limit 1600 1950 2300 ma active pull - down r pdwn - b channel dis abled 75 oscillator frequency f sw 2.5 3.0 3.5 mhz 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc).
data sheet ADP5024 rev. e | page 5 of 28 ldo specifications v in3 = (v out3 + 0.5 v) or 1.7 v (whichever is greater) to 5.5 v; c in = c out = 1 f; t j = ?40c to +125c for minimum/maximum specifications, and t a = 25c for typical specificat ions, unless otherwise noted. 1 table 4. parameter symbol test conditions/comments min typ max unit input voltage range v in3 1.7 5.5 v operating supply current bias current per ldo 2 i vin3bias i out3 = 0 a 10 30 a i o ut3 = 10 ma 60 100 a i out3 = 300 ma 165 245 a total system input current i in includes all current into avin, vin1, vin2, and vin3 ldo only i out3 = 0 a , all other channels disabled 53 a output characteristics output voltage accur acy v out3 /v out3 100 a < i out3 < 300 ma ? 1.8 +1.8 % line regulation (v out3 /v out3 )/v in3 i out3 = 1 ma ?0.03 +0.03 %/v load regulation 3 (v out3 /v out3 )/i out3 i out3 = 1 ma to 300 ma 0.001 0.003 %/ma voltage feedback v fb3 0.491 0.5 0.509 v dropout vo ltag e 4 v dropout v out3 = 5.2 v, i out3 = 300 ma 50 mv v out3 = 3.3 v, i out3 = 300 ma 75 140 v out3 = 2.5 v, i out3 = 300 ma 100 mv v out3 = 1.8 v, i out3 = 300 ma 180 mv current - limit threshold 5 i limit3 335 600 ma active pull - down r pdwn - l cha nnel disabled 600 output noise regulator ldo noise ldo 10 hz to 100 khz, v in3 = 5 v, v out3 = 2.8 v 100 v rms power supply rejection rati o psrr regulator ldo 10 khz, v in3 = 3.3 v, v out3 = 2.8 v, i out3 = 1 ma 60 db 100 khz, v in3 = 3.3 v, v out3 = 2. 8 v, i out3 = 1 ma 62 db 1 mhz, v in3 = 3.3 v, v out3 = 2.8 v, i out3 = 1 ma 63 db 1 all limits at tem perature extremes are guaranteed via correlation using standard statistical quality control (sqc). 2 this is the input current into vin3, which is not delivered to the output load. 3 based on an endpoint calculation using 1 ma and 300 ma loads. 4 dropout v oltage is defined as the input - to - output voltage differential when the input voltage is set to the nominal output voltage. this applies only to output voltages above 1.7 v. 5 current - limit threshold is defined as the current at which the output voltage dro ps to 90% of the specified typical value. for example, the current limit for a 3.0 v output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 v or 2.7 v.
ADP5024 data sheet rev. e | page 6 of 28 input and output cap acitor, recommended specifications t a = ?40c to +125c, unless otherwise specified. table 5. parameter symbol min typ max unit nominal input and output capacit or ratings buck1, buck2 input capacitor ratings c min1 , c min2 4.7 40 f buck1, buck2 output capacitor ratings c min1 , c min2 10 40 f ldo 1 input and output capacitor ratings c min3 , c min4 1. 0 f capacito r esr r esr 0.001 1 1 the minimum input and output capacitance should be greater than 0. 7 0 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. x7r - and x5r - type capacitors are recomme nded; y5v and z5u capacitors are not recommended for use be cause of their poor temperature and dc bias characteristics .
data sheet ADP5024 rev. e | page 7 of 28 absolute maximum rat ings table 6. parameter rating a vin to agnd ?0.3 v to + 6 v vin1, vin2 to avin ? 0.3 v to +0.3 v pgnd1, pgnd2 to agnd ? 0.3 v to +0.3 v vin3, vout1, vout2, fb1, fb2, fb3, en1, en2, en3, mode to a g nd ?0.3 v to ( a vin + 0.3 v) vout3 to agnd ?0.3 v to (vin 3 + 0.3 v) sw1 to pgnd1 ?0.3 v to (vin1 + 0.3 v) sw2 to pgnd2 ?0.3 v to (vin 2 + 0.3 v) storage temperature range ?65c to +150c operating junction temperature range ?40c to +125c soldering conditions jedec j - std - 020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationa l section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. for detailed information on power dissipation, see the power dissipation and therma l considerations section. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 7. thermal resistance package type ja jc unit 24 - lead , 0.5 mm pitch lfcsp 35 3 c/w esd caution
ADP5024 data sheet rev. e | page 8 of 28 pin configuration an d function descripti ons notes 1. nc = not internally connected. 2. it is recommended that the exposed pad be soldered to the ground plane. 2 1 3 4 5 6 18 17 16 15 14 13 nc pgnd2 sw2 vin2 agnd agnd mode pgnd1 sw1 vin1 avin agnd 8 9 10 11 7 fb2 vout2 vout1 fb1 12 en1 en2 20 19 21 vout3 fb3 vin3 22 en3 23 agnd 24 agnd ADP5024 top view 09888-002 figure 2 . pin configuration view from top of the die table 8. pin function descriptions pin no. mnemonic d escription 1 agnd analog ground. 2 agnd analog ground. 3 vin2 buck2 input supply (2.3 v to 5.5 v). connect vin2 to vin1 and avin. 4 sw2 buck2 switching node. 5 pgnd2 dedicated power ground for buck2. 6 nc no connect. leave this pin unconnect ed or con nect to ground . 7 en2 buck2 enable pin. high level turns on this regulator, and low level turns it off. 8 fb2 buck2 feedback input. for device models with an a djustable output voltage, connect this pin to the middle of the buck2 resistor divider . for dev ice models with a fixed output voltage, leave this pin unconnected. 9 vout2 buck2 output voltage sensing input. connect vout2 to the top of the capacitor on vout2. 10 vout1 buck1 output voltage sensing input. connect vout1 to the top of the capacitor on vout1. 11 fb1 buck 1 feedback input. for device models with an a djustable output voltage, connect this pin to the middle of the buck1 resistor divider . for device models with a fixed output voltage, leave this pin unconnected. 12 en1 buck1 enable pin. hi gh level turns on this regulator, and low level turns it off. 13 mode buck1/buck2 operating mode . mode = high for forced pwm operation. mode = low for automatic pwm/psm operation. 14 pgnd1 dedicated power ground for buck1. 15 sw1 buck1 switching node . 16 vin1 buck1 input supply (2.3 v to 5.5 v). connect vin1 to vin2 and avin. 17 avi n analog input supply (2.3 v to 5.5 v). connect avin to vin1 and vin2. 18 agnd analog ground. 19 fb3 l do feedback input. for device models with an a djustable output volta ge, connect this pin to the middle of the ldo resistor divider . for device models with a fixed output voltage, connect this pin to the top of the capacitor on vout3 . 20 vout3 ldo output voltage. 21 vin3 ldo input supply (1.7 v to 5.5 v). 22 en3 ldo ena ble pin. high level turns on this regulator, and low level turns it off. 23 agnd analog ground. 24 agnd analog ground. epad (ep) exposed pad. it is recommended that the exposed pad be soldered to the ground plane.
data sheet ADP5024 rev. e | page 9 of 28 typical performance characteristics v in1 = v in2 = v in3 = 3 . 6 v, t a = 25c, unless otherwise noted. 0 20 40 60 80 100 120 140 2.3 2.8 3.3 3.8 4.3 4.8 5.3 input vo lt age (v) quiescent current (a) 09888-003 figure 3 . system quiescent current vs. input voltage, v out1 = 3.3 v, v out2 = 1.8 v, v out3 = 1.2 v, all channels unloaded 4 1 3 t 2 ch 1 2 . 00 v ch 4 5 . 00 v m 40 . 0 s a ch 3 2 . 2 v t 11 . 20 % b w ch 2 50 . 0m a ? b w b w ch 3 5 . 00 v b w sw i o u t vout en 09888-004 figure 4 . buck1 startup, v out1 = 1 . 8 v, i out1 = 5 ma 4 1 3 t 2 ch1 2.00v ch4 5.00v m 40.0s a ch3 2.2v t 11.20% b w ch2 50.0ma ? b w b w ch3 5.00v b w sw i o u t vout en 09888-005 figure 5 . buck2 startup, v out2 = 3 . 3 v, i out2 = 10 ma 3.270 3.275 3.280 3.285 3.290 3.295 3.300 3.305 3.310 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 v out (v) i out (a) ?4 0 c +2 5 c +8 5 c 09888-006 figure 6 . buck1 load regulation across temperature , v in = 4.2 v, v out1 = 3.3 v, pwm mode 1.798 1.800 1.802 1.804 1.806 1.808 1.810 1.812 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 v out (v) i out (a) ?4 0 c +2 5 c +8 5 c 09888-007 figure 7 . buck2 load regulation across temperature, v in = 3.6 v, v out2 = 1.8 v, pwm mode 0.802 0.803 0.804 0.805 0.806 0.807 0.808 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 v out (v) i out (a) ?4 0 c +2 5 c +8 5 c 09888-008 figure 8 . buck1 load regulation across temperature , v in = 3.6 v, v out1 = 0 . 8 v, pwm mode
ADP5024 data sheet rev. e | page 10 of 28 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficienc y (%) i out (a) v in = 3.9v v in = 5.5v v in = 4.2v 09888-009 figure 9 . buck1 efficiency vs. load current, across input voltage, v out1 = 3.3 v, auto matic mode 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficienc y (%) i out (a) v in = 4.2v v in = 5.5v v in = 3.9v 09888-010 figure 10 . buck1 efficiency vs. load current, across input voltage, v out1 = 3.3 v, pwm mode 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficienc y (%) i out (a) v in = 2.3v v in = 5.5v v in = 4.2v v in = 3.6v 09888-0 1 1 figure 11 . b uck2 efficiency vs. load current, across input voltage, v out2 = 1.8 v, auto matic mode 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficienc y (%) i out (a) v in = 2.3v v in = 3.6v v in = 4.2v v in = 5.5v 09888-012 figure 12 . buck2 efficiency vs. load current, across input voltage, v out2 = 1.8 v, pwm mode 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficiency(%) i out (a) v in = 2.3v v in = 5.5v v in = 4.2v v in = 3.6v 09888-013 figure 13 . buck1 e fficiency vs. load current, across input voltage, v out1 = 0.8 v, auto matic mode 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficienc y (%) i out (a) v in = 2.3v v in = 4.2v v in = 5.5v v in = 3.6v 09888-014 figure 14 . buck1 efficiency vs. load current, across input voltage, v out1 = 0.8 v, pwm mode
data sheet ADP5024 rev. e | page 11 of 28 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficienc y (%) i out (a) ?40c +25c +85c 09888-015 figure 15 . buck1 efficie ncy vs. load current, across temperature, v in = 3. 9 v , v out1 = 3.3 v, auto matic mode 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficienc y (%) i out (a) +85c +25c ?40c 09888-016 figure 16 . buck2 efficiency vs. load current, across temperature, v out2 = 1.8 v, auto matic mode 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficienc y (%) i out (a) +85c +25c ?40c 09888-017 figure 17 . buck 1 efficiency vs. load current, across temperature, v out 1 = 0 .8 v, auto matic mode 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 0 0.2 0.4 0.6 0.8 1.0 1.2 scope frequenc y (mhz) i out (a) +85c +25c ?40c 09888-018 figure 18 . buck2 switching frequency vs. output current, across temperature, v out2 = 1.8 v, pwm mode 2 4 t 1 ch1 50mv m 4.00s a ch2 240ma t 28.40% ch2 500ma ? ch4 2.00v i sw vout sw 09888-019 figure 19 . typi cal waveforms, v out1 = 3.3 v, i out1 = 30 ma, auto matic mode 2 4 t 1 ch1 50mv m 4.00s a ch2 220ma t 28.40% b w ch2 500ma ? ch4 2.00v b w i sw vout sw 09888-020 figure 20 . typical waveforms, v out2 = 1.8 v, i out2 = 30 ma, auto matic mode
ADP5024 data sheet rev. e | page 12 of 28 2 4 t 1 ch1 50mv m 400ns a ch2 220ma t 28.40% b w ch2 500ma ? ch4 2.00v b w i sw vout sw 09888-021 figure 21 . typical waveforms, v out1 = 3.3 v, i out1 = 30 ma, pwm mode 2 4 t 1 ch1 50mv m 400ns a ch2 220ma t 28.40% b w ch2 500ma ? ch4 2.00v b w i sw vout sw 09888-022 figure 22 . typical waveforms, v out2 = 1.8 v, i out2 = 30 ma, pwm mode ch1 50.0mv ch3 1.00v ch4 2.00v m 1.00ms a ch3 4.80v 1 3 t 30.40% t b w b w b w vout vin sw 09888-023 figure 23 . buck1 response to line transient, input voltage from 4.5 v to 5.0 v, v out1 = 3.3 v, pwm mode 1 4 t 3 ch1 50.0mv ch3 1.00v ch4 2.00v m 1.00ms a ch3 4.80v t 30.40% b w b w b w vout vin sw 09888-024 figure 24 . buck2 response to line transient, v in = 4.5 v to 5.0 v, v out2 = 1.8 v, pwm mode 4 1 t 2 ch1 50.0mv ch4 5.00v m 20.0s a ch2 356ma t 60.000s b w ch2 50.0ma ? b w b w vout i out sw 09888-025 figure 25 . buck1 response to load transient, i out1 from 1 ma to 50 ma, v out1 = 3.3 v, automatic mode 4 1 t 2 ch1 50.0mv ch4 5.00v m 20.0s a ch2 379ma t 22.20% b w ch2 50.0ma ? b w b w vout i out sw 09888-026 figure 26 . buck2 response to load transient, i out2 from 1 ma to 50 ma, v out2 = 1.8 v, automatic mode
data sheet ADP5024 rev. e | page 13 of 2 8 4 2 t 1 ch1 50.0mv ch4 5.00v m 20.0s a ch2 408ma t 20.40% b w ch2 200ma ? b w b w vout i out sw 09888-027 figure 27 . buck1 response to load transient, i out1 from 20 ma to 180 ma, v out1 = 3.3 v, automatic mode 4 2 t 1 ch1 100mv ch4 5.00v m 20.0s a ch2 88.0ma t 19.20% b w ch2 200ma ? b w b w vout i out sw 09888-028 figure 28 . buck2 response to load transient, i out2 from 20 ma to 180 ma, v out2 = 1.8 v, automatic mode 4 1 3 t 2 ch1 5.00v ch4 5.00v m 400ns a ch4 1.90v t 50.00% b w ch2 5.00v b w b w ch3 5.00v b w vout1 vout2 sw1 sw2 09888-029 figure 29 . vout x and sw waveforms for buck1 and buck2 in pwm mode showing out - of - phase operation ch1 100m a ch2 5v m40 s 2.5gs/s 1m points a ch2 4.20v t 159.4 s ch3 1v 2 3 1 en v out i in 09888-030 figure 30 . ldo startup, v out3 = 1.8 v 3.294 3.295 3.296 3.297 3.298 3.299 3.300 3.301 3.302 3.303 3.304 0 0.1 0.2 0.3 v out (v) i out (a) v in = 3.8v v in = 4.2v v in = 5.5v 09888-031 figure 31 . ldo load regulation across input voltage, v out3 = 3.3 v 0 50 100 150 200 250 300 350 400 2.3 2.8 3.3 3.8 4.3 4.8 5.3 rd s on (m?) input vo l t age (v) +25c +125c ?40c 09888-032 figure 32 . nmos rds on vs. input voltage across temperature
ADP5024 data sheet rev. e | page 14 of 28 2.3 2.8 3.3 3.8 4.3 4.8 5.3 rd s on (m?) input vo l t age (v) +125c +25c ?40c 0 50 100 150 200 250 09888-033 figure 33 . pmos rds on vs. input voltage across temperature 1.792 1.793 1.794 1.795 1.796 1.797 1.798 1.799 1.800 1.801 1.802 0 0.1 0.2 0.3 v out (v) i out (a) ?4 0 c +2 5 c +8 5 c 09888-034 figure 34 . ldo load regulation across temperature, v in3 = 3.6 v, v out3 = 1.8 v 0 0.5 1.0 1.5 2.0 2.5 3.0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 v in (v) i out = 300m a i out = 150m a i out = 100m a i out = 1m a i out = 10m a i out = 100 a 09888-035 v out (v) figure 35 . ldo line regulation across output l oad, v out3 = 2.8 v 0 0.05 0.10 0.15 0.20 0.25 ground current (a) load current (a) 0 5 10 15 20 25 30 35 40 45 50 09888-036 figure 36 . ldo ground current vs. output load, v in3 = 3.3 v, v out3 = 2.8 v 2 t 1 ch1 100mv m 40.0s a ch2 52.0ma t 19.20% b w ch2 100ma ? b w vout i out 09888-037 figure 37 . ldo response to load transient, i out3 from 1 ma to 80 ma, v out3 = 2.8 v 2 3 t 1 ch1 20.0mv ch3 1.00v m 100s a ch3 4.80v t 28.40% vout vin 09888-038 figure 38 . ldo response to line transient, input voltage from 4.5 v to 5 v, v out3 = 2.8 v
data sheet ADP5024 rev. e | page 15 of 28 60 55 50 45 40 35 30 25 0.001 0.01 0.1 1 10 100 i load (ma) rms noise (v) v in = 3.3v v in = 5v 09888-039 figure 39 . ldo output noise vs. load current, across input voltage, v out3 = 2.8 v 60 65 55 50 45 40 35 30 25 0.001 0.01 0.1 1 10 100 i load (ma) rms noise (v) v in = 3.3v v in = 5v 09888-040 figure 40 . ldo o utput noise vs. load current, across input voltage, v out3 = 3.0 v 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 100a 1ma 10ma 50ma 100ma 150ma 09888-041 figure 41 . ldo psrr across output l oad, v in3 = 3.3 v, v out3 = 2 .8 v 0 ?20 ?40 ?60 ?80 ?100 ?120 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 100a 1ma 10ma 50ma 100ma 150ma 09888-042 figure 42 . ldo psrr across output load, v in3 = 3.3 v, v o ut3 = 3 .0 v 0 ?20 ?40 ?60 ?80 ?100 ?120 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 100a 1ma 10ma 50ma 100ma 150ma 09888-043 figure 43 . ldo psrr across output loa d, v in3 = 5.0 v, v out 3 = 2.8 v 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 100a 1ma 10ma 50ma 100ma 150ma 09888-044 figure 44 . ldo psrr across output lo ad, v in3 = 5.0 v, v out3 = 3.0 v
ADP5024 data sheet rev. e | page 16 of 28 theory of operation ldo control ldo undervoltage lockout soft start pwm/ psm control buck2 driver and antishoot through soft start driver and antishoot through oscillator thermal shutdown system undervoltage lockout pwm comp gm error amp gm error amp psm comp psm comp low current i limit pwm comp low current i limit r1 r2 ADP5024 v out1 v out2 vin1 avin sw1 pgnd1 vin3 agnd vout3 fb3 pgnd2 sw2 vin2 av i n 75 ? enbk1 enable and mode control en1 enbk1 enbk2 enldo 75 ? enbk2 en2 en3 600 ? enldo b sel op mode mode2 a y mode fb1 fb2 pwm/ psm control buck1 09888-045 figure 45. functional block diagram
data sheet ADP5024 rev. e | page 17 of 28 power management uni t the ADP5024 is a micropower management unit (micro pmu) combing two step - down (buck) dc - to - dc convertors and one low dropout linear regulat or (ldo). the high switching frequency and tiny 24 - lead lfcsp package allow for a s mall power manage - ment solution. to combine these high performance regulators into the micropmu , there is a system controller allowing them to operate together. the buck re gulators can operate in forced pwm mode if the mode pin is at a logic level high . in forced pwm mode, the buck switching frequency is always constant and does not change with the load current. if the mode pin is at logic level low , the switching regulators operate in auto matic pwm/psm mode. in this mode, the regulators operate at a fixed pwm frequency when the load current is above the psm current threshold. when the load current falls below the psm current threshold, the regulator in question enters psm, w here the switching occurs in bursts. the burst repetition rate is a function of the current load and the output capacitor value. this operating mode reduces the switching and quiescent current losses. the auto matic pwm/psm mode transition is controlled ind ependently for each buck regulator. the two bucks operate synchronized to each other. the ADP5024 has individual enable pins (en 1 to en3 ) that control the activation of each regulator. the regula tors are activated by a logic level high applied to the respective en pin , wherein en1 controls buck1, en2 controls buck2, and en3 controls the ldo. regulator output voltages are set through external resistor dividers or can be optionally factory programm ed to default values (see the ordering guide section). when a regulator is turned on, the output voltage ramp rate is controlled though a soft start circuit to avoid a large inrush current due to the charging of the output capaci tors. thermal protection in the event that the junction temperature rises above 150c, the thermal shutdown circuit turns off all of the regulators. extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient tempera - ture. a 20c hysteresis is included so that when thermal shutdown occurs, the regulators do not return to operation until the on - ch ip temperature drops below 130c. when emerging from ther mal shutdown, all regulators re start with soft start control. undervoltage lockout to protect against battery discharge, undervoltage lockout (uvlo) circuitry is integrated in the system. if the input voltage on av in drops below a typical 2.15 v uvlo threshold, all channels shut down. in the buck chan nels, both the power switch and the synchronous rectifier turn off. when the voltage on av in rises above the uvlo threshold, the part is enabled once more. alternatively, the user can select device models with a uvlo set at a higher level, suitable for 5 v supply applications. for these models, the device reaches the turn off th reshold when the input supply drops to 3.65 v typical. in case of a thermal or uvlo event, the active pull - downs (if factory enabled) are enabled to discharge the output capacitors q uickly. the pull - down resistor s remain engaged until the thermal fault event is no longer present or the input supply voltage falls below the v por voltage level. the typical value of v por is approx - imately 1 v . enable/shutdown the ADP5024 has an individual control pin for each regulator. a logic level high applied to the enx pin activates a regulato r whereas a logic level low turns off a regulator. figure 46 shows the r egulator activation timings for the ADP5024 when all enable pins are connected to avin. also shown is the active pull - down activation.
ADP5024 data sheet rev. e | page 18 of 28 avin vout3 vout1 v uvlo vout2 v por buck2 pull-down buck1, ldo pull-downs 50s (min) 30s (min) 50s (min) 30s (min) 09888-046 figure 46. regulator sequencing ( en1 = en2 = en3 = v avin )
data sheet ADP5024 rev. e | page 19 of 28 buck1 and buck2 the buck uses a fixed frequency and high speed current mode architecture. the buck operates with an input voltage of 2.3 v to 5.5 v. the buck output voltage is set through external resistor dividers, shown in figure 47 for buck1. the output voltage can optionally be factory programmed to default values , as indicated in the ordering guide section. in this event, r1 and r2 are not needed, and fb1 can remain u nconnected. in all cases, vout1 must be connected to the output capacitor. fb1 is 0.5 v. buck agnd fb1 sw1 r1 r2 vout1 vout1 vin1 l1 1h c5 10f v out1 = v fb1 + 1 r1 r2 09888-047 figure 47 . buck1 external output voltage setting control scheme the bucks operate with a fixed frequency, current mode pwm control architect ure at medium to high loads for high efficiency, but shift to a power save mode (psm) control scheme at light loads to lower the regulation power losses. when operating in fixed frequency pwm mode, the duty cycle of the integrated switches is adjusted and regulates the output voltage. when operating in psm at light loads, the output voltage is controlled in a hysteretic manner, with higher output voltage ripple. dur ing part of this time, the converter is able to stop switching and enters an idle mode, which improves conversion efficiency. pwm mode in pwm mode, the bucks operate at a fixed frequency of 3 mhz , set by an internal oscillator. at the start of each oscillator cycle, the pfet switch is turned on, sending a positive voltage across the inductor. curr ent in the inductor increases until the current sense signal crosses the peak inductor current threshold , which turns off the pfet switch and turns on the nfet synchronous rectifier. this sends a negative voltage across the inductor, causing the inductor c urrent to decrease. the synchronous rectifier stays on for the remainder of the cycle. the buck regulates the output voltage by adjusting the peak inductor current threshold. power save mode (psm) the bucks smoothly transition to psm operation when the loa d current decreases below the psm current threshold. when either of the bucks enters psm, an offset is induced in the pwm regulation level, which makes the output voltage rise. when the output voltage reaches a level approximately 1.5% above the pwm regula tion level, pwm operation is turned off. at this point, both power switches are off, and the buck enters an idle mode. the output capacitor discharges until the output voltage falls to the pwm regulation voltage, at which point the device drives the induct or to make the output voltage rise again to the upper threshold. this process is repeated while the load current is below the psm current threshold. the ADP5024 has a dedicated mode pin controlli ng the psm and pwm operation. a logic level high applied to the mode pin forces both bucks to operate in pwm mode. a logic level low sets the bucks to operate in auto matic psm/pwm. psm current threshold the psm current threshold is set to100 ma. the bucks employ a sche me that enables this current to remain accurately controlled, independent of input and output voltage levels. this scheme also ensures that there is very little hysteresis between the psm current threshold for entry to and exit from the psm. the psm current threshold is optimized for excellent efficiency over all load currents. oscillator/phasing of inductor switching the ADP5024 ensures that both bucks operate at the same switching frequency when both bucks are in pwm mode. additionally, the ADP5024 ensures that when both bucks are in pwm mode, they operate out of phase, whereby the buck2 p fet starts conducting exactly half a clock period after the buck1 p fet starts conducting. short - circuit protection the bucks include frequency foldback to prevent output current runaway on a hard short. when the voltage at the feedback pin falls below half the target output voltage, indica ting the possi - bility of a hard short at the output, the switching frequency is reduced to half the internal oscillator frequency. the reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output curre nt. soft start the bucks have an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. this prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. current limit each buck has protection circuitry to limit the amount of positive current flowing through the pfet switch and the amount of negative current flowing through the synchronous rectifier. the positive current limit on the power switch limits the amount of current that can flow from the input to the output. the negative current limit prevents the inductor current from reversing direction and flowing out of the load. 100% duty operation with a drop in i nput voltage, or with an increase in load current, the buck may reach a limit where, even with the pfet switch on 100% of the time, the output voltage drops below the
ADP5024 data sheet rev. e | page 20 of 28 desired output voltage. at this limit, the buck transitions to a mode where the pfet swit ch stays on 100% of the time. when the input conditions change again and the required duty cycle falls, the buck immediately restarts pwm regulation without allowing overshoot on the output voltage. active pull - down resistor s all regulators have optional, factory programmable, active pull - down resistors discharging the respective output capacitors when the regulators are disabled. the pull - down resistors are connected between voutx and agnd. active pull - downs are disabled when the regulators are turned on. the typical value of the pull - down resistor is 600 for the ldo and 75 for each buck. figure 46 shows the activation timings for the active pull - downs during regulator activation and deactivation. ldo the ADP5024 contains one ldo with low quiescent current and low dropout voltage and provides up to 300 ma of output current. drawing a low 10 a quiescent current (typical) at no load make s the ldo i deal for battery - operated portable equipme nt. the ldo operates with an input voltage of 1.7 v to 5.5 v. the wide operating range mak es th e ldo su itable for cascading configurations where the ldo supply voltage is provided from one of the buck regulators. the ldo output voltage is set through exter nal resistor dividers , as shown in figure 48 . the output voltage can optionally be factory programmed to default values , as indicated in the ordering guide sec tion. in this event, ra and rb are not need ed, and fb3 must be connected to the top of the capacitor on vout3 . fb3 is 0.5 v. ldo fb3 ra rb vout3 vout3 vin3 c7 1f v out3 = v fb3 + 1 ra rb 09888-048 figure 48 . ldo external output voltage setting the ldo also provide s high power supply rejection ratio (psrr), low output noise, and excellent line and load transient response with only a small 1 f ceramic input and output capacitor.
data sheet ADP5024 rev. e | page 21 of 28 applications informa tion buck external compon ent selection trade - offs between performance parameters such as efficiency and transient response can be made by varying the choice of external components in the applications circuit, as shown in figure 1 . feedback resistors for the adjustable model, shown in figure 47, the total combined resistance for r1 and r2 is not to exceed 400 k?. inductor the high switching frequency of the ADP5024 bucks allows for the selection of small chip inductors. for best performance, use inductor values between 0.7 h and 3 h. suggested induc tors are shown in table 9 . the peak - to - peak inductor current ripple is calculated using the following equation: l f v v v v i sw in out in out ripple ? = ) ( where: f sw is the switching frequency. l is the inductor value. the minimum dc current rating of the inductor must be greater than the inductor peak current. the inductor peak current is calculated using the following equation: 2 ) ( ripple max load peak i i i + = inductor conduction losses are caused by the flow of current through the inductor, which has an ass ociated internal dc resistance (dcr). larger sized inductors have smaller dcr, which may decrease inductor conduction losses. inductor core losse s are related to the magnetic permeability of the core mate rial. because the bucks are high switching frequency dc - to - dc converters, shielded ferrite core material is recommended for its low core losses and low emi. output capacitor higher output capacitor values reduce the output voltage ripple and improve load transient response. when choosing this value, it is also important to account for the loss of capacitance due to output voltage dc bias. ceramic capacitors are manufactured with a variety of dielec - trics, ea ch with a different behavior over temperature and applied voltage. capacitors must have a dielectric that is adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage ra ting of 6.3 v or 10 v are recom mended for best per - formance. y5v and z5u dielectrics are not recommended for use with any dc - to - dc converter because of their poor temperature and dc bias characteristics. the worst - case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calcu - lated using the following equation : c eff = c out (1 ? tempco ) (1 ? tol ) where: c eff is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example, the worst - case temperature coefficient (t empco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10% , and c out is 9.2 f at 1.8 v, as shown in figure 49. substituting these values in the equation yield s c eff = 9.2 f (1 ? 0.15 ) (1 ? 0.1) 7.0 f to guarantee the performance of the bucks, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. 0 2 4 6 8 10 12 0 1 2 3 4 5 6 dc bias voltage (v) capacitance (f) 09888-049 figure 49 . capacitance vs. voltage characteristic table 9. suggested 1.0 h inductors vendor model dimensions (mm) i sat (ma) dcr (m) murata lqm2mpn1r0ng0b 2.0 1.6 0.9 1400 85 murata lq h32pn1r0nn0 3.2 2.5 1.6 2300 45 taiyo yuden cbc3225t1r0mr 3.2 2.5 2.5 2000 71 coilcraft xfl4020 - 102me 4.0 4.0 2.1 5400 11 coilcraft xpl2010 - 102ml 1.9 2.0 1.0 1800 89 toko mdt2520 - cn 2.5 2.0 1.2 1350 85
ADP5024 data sheet rev. e | page 22 of 28 the peak - to - peak output voltage ripple for the selected o utput capacitor and inductor values is calculated using the following equation: ( ) out sw in out sw ripple ripple c l f v c f i v = 2 2 8 capacitors with lower equivalent series resistance (esr) are preferred to guarantee low output voltage ripple, as shown in the following equation: ripple ripple cout i v esr the effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 7 f and a maximum of 40 f. the buck regulators require 10 f output capacitors to guarantee stability and response to rapid l oad variations and to transition into and out of the pwm/psm modes. a list of suggested capaci - tors is shown in table 10 . in certain applications where one or both buck regulator powers a processor, the operating state is known be cause it is controlled by software. in this condition, the processor can drive the mode pin according to the operating state; consequently, it is possible to reduce the output capacitor from 10 f to 4.7 f because the regulator does not expect a large loa d variation when working in psm mode (see figure 50 ). input capacitor higher value input capacitors help to reduce the input voltage ripple and improve transient response. maximum input capacitor current is calculated using the following equation: in out in out max load cin v v v v i i ) ( ) ( ? to minimize supply noise, place the input capacitor as close as possible to the vinx pin of the buck. as with the output capa - citor, a low esr capacitor is recommended. a 4.7 f capacitor is recommended for a typi cal application; dependin g on the application, a smaller or larger output capacitor may be chosen. a list of suggested 4.7 f capacitors is shown in table 11. the effective capacitance needed for stability, which includes temperat ure and dc bias effects, is a minimum of 3 f and a maximum of 10 f. table 10. suggested 10 f capacitors vendor type model case sie voltage rating v murata x5r grm188r60j106 0603 6.3 tdk x5r c1608jb0j106k 0603 6.3 panasonic x5r ecj1vb0j106m 0603 6.3 table 11. suggested 4.7 f capacitors vendor type model case sie voltage rating v murata x5r grm188r60j475me19d 0402 6.3 taiyo yuden x5r jmk107bj475 0402 6.3 panasonic x5r ecj - 0eb0j475m 0402 6.3 tab le 12. suggested 1.0 f capacitors vendor type model case sie voltage rating v murata x5r grm155b30j105k 0402 6.3 tdk x5r c1005jb0j105kt 0402 6.3 panasonic x5r ecj0eb0j105k 0402 6.3 taiyo yuden x5r lmk105bj105mv - f 0402 10.0 vin1 vin3 en1 pwm psm/pwm 2.3v to 5.5v sw1 fb1 r2 r1 vout1 pgnd1 mode c5 10f v out1 at 1200ma l1 1h en1 buck1 mode c3 1f c2 4.7f c1 4.7f avin c avin 0.1f vin2 en2 agnd en2 buck2 mode en3 1.7v to 5.5v on off on off en3 ldo (analog) ADP5024 housekeeping sw2 fb2 r4 r3 vout2 pgnd2 c6 10f v out2 at 1200ma l2 1h fb3 r6 r5 vout3 c7 1f v out3 at 300ma 09888-050 figure 50 . processor system power management with psm/pwm control
data sheet ADP5024 rev. e | page 23 of 28 ldo external compone nt selection feedback resistors for the adjustable model, the maximum value of rb must not exceed 200 k? (see fi gure 48). output capacitor the ADP5024 ldo is designed for operation with small, space - saving ceramic capacitors, but functions with most commonly used capacitors as long as care is taken with t he esr value. the esr of the out put capacitor affects stability of the ldo control loop. a minimum of 0.70 f capacitance with an esr of 1 ? or less is recommended to ensure stability of the ADP5024 . transient response to chang es in load current is also affected by output capacitance. using a larger value of output capacitance improves the transient response of the ADP5024 to large changes in load current. input bypas s capacitor connecting a 1 f capacitor from vin3 to ground reduces the cir cuit sensitivity to printed circuit board (pcb) layout, especially when encountering long in put traces or high source imped ance. if greater than 1 f of output capacitance is requir ed, increase the input capacitor to match it. input and output capacitor properties use any good quality ceramic capacitors with the ADP5024 as long as they meet the minimum capacitance and maxim um esr requirements. ceramic capacitors are manufactured with a variety of dielectr ics, each with a different behavior over temper - ature and applied voltage. capacitors must have a dielectric that is adequate to ensure the minimum capacitance over the nece ssary tempera ture range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended for best perfor mance. y5v and z5u dielectrics are not recommended for use with any ldo because of their poor temperature and dc bi as characteristics. figure 51 depicts the capacitance vs. voltage bias characteristic of a 0402 1 f, 10 v, x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating . in general, a capacitor in a larger package or higher voltag e rating exhibits better stability. the temperature variation of the x5r dielectric is about 15% over the ?40c to +85c tempera - ture range and is not a function of package or voltage rating. 1.2 1.0 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 6 dc bias voltage (v) capacitance (f) 09888-051 fig ure 51 . capacitance vs. voltage characteristic use the following equation to determine the worst - case capa - citance accounting for capacitor variation over temperature, component tolerance, and voltage. c eff = c bias (1 ? tempco ) (1 ? tol ) where: c bias is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example, the worst - case temperature coefficient (tempco) over ?40 c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10% , and c bias is 0. 85 f at 1.8 v , as shown in figure 51. substituting these values into the following equation yields : c eff = 0. 85 f (1 ? 0.15) (1 ? 0.1) = 0. 65 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over temperature and tolerance at the chosen output voltage. to guarantee the pe rformance of the ADP5024 , it is imperative that the effects of dc bias, temperature, and toler ances on the behavior of the capacitors be evaluated for each application.
ADP5024 data sheet rev. e | page 24 of 28 power dissipation an d thermal considerat ions th e ADP5024 is a highly efficient micropower management unit (micropmu) , and, in most cases, the power dissipated in the device is not a concern. however, if the device operates at hig h ambient tem peratures and maxi mum loading condition, the junction temperature can reach the maximum allowable operating limit (125 c). when the temperature exceeds 150c, the ADP5024 turns off all of the reg ulators allowing the device to cool down. when the die temperature falls below 130c, the ADP5024 resumes normal operation. this section provides guidelines to calculate the power dissi - pated in the device and ensure that the ADP5024 operates below the maximum allowable junction temperature. the efficiency for each regulator on the ADP5024 is given by 100% = in out p p (1) where: is the efficiency. p in is the input power. p out is the output power. power loss is given by p loss = p in ? p out (2a) or p loss = p out (1? )/ (2b) power dissipation can be calculated in several ways. the most intuitive and practical is to measure the pow er dissipated at the input and at all of the outputs. perform the measurements at the worst - case conditions (voltages, currents, and temperature). the difference between input and output power is dissipated in the device and the inductor. use equation 4 to derive the power lost in the inductor, and from this result use equation 3 to calculate the power dissipation in the ADP5024 buck converter. a second method to estimate the power dissipation use s the effi - ci ency curves provided for the buck regulator, and the power lost on the ldo can be calculated using equation 12. when t he buck efficiency is known, use equation 2b to derive the total power l ost in the buck regulator and inductor, use equa - ti on 4 to derive the power lost in the inductor, and then calculate the power dissipation in the buck converter using equation 3. add the power dissipated in the buck and in the ldo to find the total dissipated power. note that the buck efficiency curves are t ypical values and may not be provided for all possible combinations of v in , v out , and i out . to account for these variations , it is necessary to include a safety margin when calculating the power dissipated in the buck. a third way to estimate the power di ssipation is analytical and involves modeling the losses in the buck circuit provided by equation 8 to equation 11 and calculating the losses in the ldo provided by equation 12. buck regulator power dissipation the power loss of the buck regulator is appr oximated by p loss = p dbuck + p l (3) where: p dbuck is the power dissipation on one of the ADP5024 buck regulators. p l is the inductor power loss. the inductor losses are external to the device an d they do not have any effect on the die temperature. the inductor losses are estimated (without core losses) by p l i out1( rms) 2 dcr l (4) where: dcr l is the inductor series resistance. i out1(rms) is the rms load current of the buck regulator. 12 + 1 ) ( r i i out1 rms out1 = (5) where r is the normalized inductor ripple current . r = v out1 (1 ? d )/( i out1 l f sw ) (6) where: l is the inductance. f sw is the switching frequency. d is the duty cycle. d = v out1 / v i n1 (7) the buck regulator power dissipation, p dbuck , of the ADP5024 includes the power switch conductive los ses, the switch losses, and the transi tion losses of each channel. there are other sources of loss, but these are generally less significant at high output load currents, where the thermal limit of the applicati on is l ocated . equation 8 captures the calcu lation that must be made to estimate the power dissipation in the buck regulator. p dbuck = p cond + p sw + p tran (8) the power switch conductive losses are due to the output current, i out1 , flowing through the p - mosfet and the n - mosfet power switches that ha ve internal resistance, rds on - p and rds on - n . the amount of conductive power loss is found by p cond = [ rds on - p d + rds on - n (1 ? d )] i out1 ( rms) 2 (9) where rds on - p is approximately 0.2 ?, and rds on - n is approxi - mately 0.16 ? at a junction temperatu re of 25c and v in1 = v in2 = 3.6 v. at v in1 = v in2 = 2.3 v, these values change to 0.31 ? and 0.21 ?, respectively, and at v in1 = v in2 = 5.5 v, the values are 0.16 ? and 0.14 ?, respectively.
data sheet ADP5024 rev. e | page 25 of 28 switching losses are associated with the current drawn by the driver t o turn on and turn off the power devices at the switching frequency. the amount of switching power loss is given by p sw = ( c gat e - p + c gate - n ) v in1 2 f sw (10) where: c gate - p is the p - mosfet gate capacitance. c gate - n is the n - mosfet gate capacitance. for the ADP5024 , the total of ( c gate - p + c gate - n ) is approx - imately 15 0 p f. the transition losses occur because the p - channel power mosfet cannot be turned on or off instantaneously, and the sw node takes some time to slew from near ground to near v out1 (and from v out1 to ground). the amount of transition loss is calculated by p tran = v in1 i o ut 1 ( t rise + t fall ) f sw (11) where t rise and t fall are the rise time and the fall time of the switching node, sw. for the ADP5024 , the rise and fall times of sw are in the order of 5 ns. if the preceding equations and parameters are used for estimat ing the converter efficiency, it must be noted that the equations do not describe all of the converter losses, and the parameter values given are typical numbers. the converter p erformance also depends on the choice of passive components and board layout; therefore, include a sufficient safety margin i n the estimate. ldo regulator power dissipation the power loss of the ldo regulator is given by p dldo = [( v in ? v out ) i load ] + ( v in i gnd ) (12) where: i load is the load current of the ldo regulator. v in and v out are input and output voltages of the ldo, respectively. i gnd is the ground current of the ldo regulator. power dissipation due to the ground current is smal l , and it can b e ignored. junction temperature in cases where the board temperature , t a , is known, the thermal resistance parameter, ja , can be used to estimate the junction temperature rise. t j is calculated from t a and p d using the formula t j = t a + ( p d ja ) (14) the typical ja value for the 24 - lead, 4 mm 4 mm lfcsp is 35c/w (see table 7 ). a very important factor to consider is that ja is based on a 4 - layer , 4 in 3 in, 2.5 oz copper, as per jedec standard, and real applications may use different sizes and layers . to remove heat from the device, it is impor tant to maximize the use of copper. copper exposed to air dissipates heat better than copper used in the inner layers. connect the exposed pad to the ground plane with several vias. if the case temperature can be measured, the junction temperature is calcu lated by t j = t c + ( p d jc ) (15) where t c is the case temperature and jc is the junction - to - case thermal resistance provided in table 7 . when designing an application for a particular ambient temperature range, calculate the expected ADP5024 power dissipation (p d ) due to the losses of all channels by using equation 8 to equation 13. from this power calculation, the junction temperature, t j , can be estimated using equation 14. the reliable oper ation of the converter and the ldo regulator c an be achieved only if the estimated die junction temp erature of the ADP5024 ( see equation 14) is less than 125c. reliability and mean time between failures (mtbf) is highly affected by increasing the junction temperature. additional information about product reliability can be found from the adi reliability handbook , which is available at the following url: www.analog.com/reliability_handbook . the total power dissipation in the ADP5024 simplifies to p d = p dbuck 1 + p dbuck 2 + p dld o (13)
ADP5024 data sheet rev. e | page 26 of 28 pcb layout guideline s poor layout can affect ADP5024 performance, causing electro - magnetic in terference (emi) and electromag netic compatibility (emc) problems, ground bounce, and voltage losses. poor layout can also affect regulation and stabi lity. a good layout is implemented using the following guidelines. also, refer to user guide ug - 271. ? place the inductor, input capacitor, and output capacitor close to the ic using short tracks. these components carry high switching frequencies, and large tracks act as antennas. ? route the output voltage path away from the inductor and sw node to minimize noise and magnetic interference. ? maximize the size of ground metal on the component side to help with thermal dissipation. ? use a ground plane with several vias connect ed to the com pone nt side ground to further reduce noise interference on sensitive circuit nodes. ? connect vin1, vin2, and avin together close to the ic using short tracks.
data sheet ADP5024 rev. e | page 27 of 28 typical application sche matics vin1 vin3 en1 pwm psm/pwm 2.3v to 5.5v sw1 fb1 vout1 pgnd1 mode c5 10f v out1 at 1200ma l1 1h en1 buck1 mode c3 1f c2 4.7f c1 4.7f avin c avin 0.1f vin2 en2 agnd en2 buck2 mode en3 1.7v to 5.5v on off on off en3 ldo (analog) ADP5024 housekeeping sw2 fb2 vout2 pgnd2 c6 10f v out2 at 1200ma l2 1h fb3 vout3 c7 1f v out3 at 300ma 09888-052 figure 52 . fixed output voltages with enable pins vin1 vin3 en1 pwm psm/pwm 2.3v to 5.5v sw1 fb1 r2 r1 vout1 pgnd1 mode c5 10f v out1 at 1200ma l1 1h en1 buck1 mode c3 1f c2 4.7f c1 4.7f avin c avin 0.1f vin2 en2 agnd en2 buck2 mode en3 1.7v to 5.5v on off on off en3 ldo (analog) ADP5024 housekeeping sw2 fb2 r4 r3 vout2 pgnd2 c6 10f v out2 at 1200ma l2 1h fb3 r6 r5 vout3 c7 1f v out3 at 300ma 09888-053 figure 53 . adjustable output voltages with enable pins bill of materials table 13. reference value part number vendor package or dimension (mm) c avin 0.1 f, x5r, 6.3 v jmk105bj104mv - f tai yo - yude n 0402 c3, c7 1 f, x5r, 6.3 v lmk105bj105mv - f tai yo - yude n 0402 c1, c2 4.7 f, x5r, 6.3 v ecj - 0eb0j475m panasonic - ecg 0402 c5, c6 10 f, x5r, 6.3 v jmk107bj106ma - t tai yo - yude n 0603 l1, l2 1 h, 0.18 , 850 ma brc1608t1r0m tai yo - yude n 0603 1 h, 0.085 , 1400 ma lqm2mpn1r0ng0b murata 2.0 1.6 0.9 1 h, 0.059 , 900 ma epl2014 - 102ml coilcraft 2.0 2.0 1.4 1 h, 0.086 , 1350 ma mdt2520 - cn toko 2.5 2.0 1.2 ic1 th ree - regulator micropmu ADP5024 analog devices 24- lead lfcsp
ADP5024 data sheet rev. e | page 28 of 28 outline dimensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.20 compliant to jedec standards mo-220-wggd-8. 06-11-2012-a bottom view top view exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 seating plane 0.80 0.75 0.70 0.20 ref 0.25 min coplanarity 0.08 pin 1 indicator 2.20 2.10 sq 2.00 1 24 7 12 13 18 19 6 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.05 max 0.02 nom figure 54. 24-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-24-10) dimensions shown in millimeters ordering guide model 1 temperature range output voltage 2 uvlo 3 active pull-down 4 package description package option ADP5024acpz-r2 ?40c to +125c adjustable low enabled on buck channels 24-lead lead frame chip scale package [lfcsp_wq] cp-24-10 ADP5024acpz-r7 ?40c to +125c adjustable low enabled on buck channels 24-lead lead frame chip scale package [lfcsp_wq] cp-24-10 ADP5024acpz-1-r7 ?40c to +125c vout1 = 1.2 v vout2 = 3.3 v vout3 = 2.8 v low enabled on buck channels 24-lead lead frame chip scale package [lfcsp_wq] cp-24-10 ADP5024acpz-2-r7 ?40c to +125c adjustable high enabled on all channels 24-lead lead frame chip scale package [lfcsp_wq] cp-24-10 ADP5024cp-evalz evaluation board for ADP5024acpz-r7 1 z = rohs compliant part. 2 for additional options, contact a local sales or distribution representative. additional options available are: buck1 and buck2: 3.3 v, 3.0 v, 2.8 v, 2.5 v, 2.3 v, 2.0 v, 1.8 v, 1.6 v, 1.5 v, 1.4 v, 1.3 v, 1.2 v, 1.1 v, 1.0 v, 0.9 v or adj ustable. ldo: 3.3 v, 3.0 v, 2.8 v, 2.5 v, 2.25 v, 2 v, 1.8 v, 1.7 v, 1.6 v, 1.5 v, 1.2 v, 1.1 v, 1.0 v, 0.9 v, 0.8 v or adjustable. 3 uvlo: low or high. 4 buck1, buck2, ldo: active pull-down resistor is programmable to be either enabled or disabled. ?2011C2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09888-0-5/13(e)

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